Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

ABSTRACT

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a β line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a γ line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an α line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a βγβ jog; a βαβ jog; and αβγ jog; a γβα jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

DOMESTIC PRIORITY

This application is a DIVISIONAL of U.S. patent application Ser. No.15/172,265, filed Jun. 3, 2016, the contents of which are incorporatedby reference herein in its entirety.

BACKGROUND

The present invention generally relates to methods of forming asemiconductor device and methods of patterning a semiconductor device.More particularly, the present invention relates to a self-alignedquadruple patterning process for forming a semiconductor device thatincludes a multi-track jogged layout.

As the technology nodes scale down to 14 nm and beyond, self-alignedmultiple patterning processes are being considered as practicalsolutions for the manufacturing process, wherein a conventionallithographic process is enhanced to produce multiple times the number ofexpected features. For example, the simplest case of multiple patterningis commonly referred to as Double Patterning Lithography (DPL), whichproduces double the expected number of features. Compared withLitho-Etch-Litho-Etch processes (LELE) used in prior technology nodes,multiple patterning processes provides better overlay tolerances.Self-Aligned Quadruple Patterning (SAQP) is considered an extension ofDPL and is expected to be one of the major solutions for future processrequirements after the 16 nm/14 nm technology node. SAQP is an advancedpatterning approach that uses pitch splitting to further extend thecapability of traditional lithography. It is targeted for implementationfor both the front end of line (FEOL) fin patterning and back end ofline (BEOL) Metal 1 layers.

Critical BEOL manufacturing patterning at 7 nm technology node requiressub-36 nanometer (nm) pitches necessitating the use of either extremeultraviolet (EUV) lithography or 193 nm-immersion-lithography based SAQPprocesses. With enormous challenges being faced in getting EUVlithography ready for production, SAQP is being considered as anoptional approach for manufacturing grid patterning for most of theindustry. In contrast to the front end of line (FEOL) fin patterning,which has successfully deployed SAQP since 10 nm node technology, BEOLmanufacturing SAQP is challenging owing to the required usage ofsignificantly lower temperature budgets for film stack deposition.

SUMMARY

Disclosed herein are interconnect structures including multi-track jogsproduced by a self-aligned quadruple patterning process having a pitchless than 40 nm and processes for forming the interconnect structures.In one or more embodiments, the self-aligned quadruple patterningprocess includes patterning a top mandrel layer disposed on a barrierlayer to form a plurality of top mandrel line features and spacestherebetween; forming a top spacer structure with a top dielectricmaterial adjacent to sidewalls of the top mandrel features; andbackfilling the spaces with a top non-mandrel material, wherein the topnon-mandrel material is selected to be etch selective relative to thetop spacer structure and the top mandrel layer.

In one or more embodiments, the process includes providing a structureincluding an interlayer dielectric, top and bottom mandrel layers, andbarrier layers therebetween; patterning a top mandrel layer to form aplurality of top mandrel line features and spaces therebetween; cuttingat least one of the top mandrel line features to provide a gapcorresponding to a γ jog; forming a top spacer structure with a topdielectric material adjacent to sidewalls of the top mandrel featuresand in the gap; wherein the gap is smaller than two times a thickness ofthe top spacer structure; and filling the gap with the top dielectricmaterial; and backfilling the spaces with a top non-mandrel material,wherein the top non-mandrel material is selected to be etch selectiverelative to the top spacer structure and the top mandrel layer.

The interconnect structures include three types of lines: a β linedefined by a patterned bottom mandrel formed in the self-alignedquadruple patterning process; a γ line defined by location underneath atop mandrel formed in the self-aligned quadruple patterning process; andan α line defined by elimination located underneath neither the topmandrel or the bottom mandrel formed in the self-aligned quadruplepatterning process.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with theadvantages and the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The forgoing and other features, and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 schematically illustrates a top down structure of an exemplaryinterconnect routing layout including multiple jogged tracks produced bya self-aligned quadruple patterning process;

FIG. 2A is a top down view and FIG. 2B is a cross sectional view takenalong lines 2B-2B after etching the top mandrel layer;

FIG. 3A is a top down view and FIG. 3B is a cross sectional view takenalong lines 3B-3B after top mandrel tip definition;

FIG. 4A is a top down view and FIG. 4B is a cross sectional view takenalong lines 4B-4B after top spacer deposition, etching, and backfill oftop non-mandrel space;

FIG. 5A is a top down view and FIG. 5B is a cross sectional view takenalong lines 5B-5B after etching of top non-mandrel backfill to providetip definition;

FIG. 6A is a top down view and FIG. 6B is a cross sectional view takenalong lines 6B-6B after top non-mandrel space backfill cut and refill;

FIG. 7A is a top down view and 7B is a cross sectional view taken alonglines 7B-7B after top non-mandrel and top mandrel pull(s);

FIG. 8A is a top down view and FIGS. 8B, 8C are cross sectional viewstaken along lines 8B-8B and 8C-8C after bottom mandrel etch;

FIG. 9A is a top down view and FIG. 9B is a cross sectional view takenalong lines 9B-9B after bottom mandrel tip definitions; and

FIG. 10A is a top down view and FIG. 10B is a cross sectional view takenalong lines 10B-10B after bottom spacer deposition, etch back and bottommandrel pull.

DETAILED DESCRIPTION

The present disclosure provides for methods for forming a semiconductordevice that includes a multi-track jogged layout such as may be desiredfor BEOL manufacturing patterning at 7 nm technology node requiringsub-40 nm pitches. Increased alignment tolerances in patterning the jogis provided by the use of single cuts in a self-aligned quadruplepatterning scheme to enable a multi-track jog. Additionally, the presentdisclosure provides a method for integrating all of the various optionsfor jogs in the self-aligned quadruple pattering scheme, i.e., thedifferent options for which specific lines are connected in the jog,thereby increasing intra-level density.

Although the following description and drawings of the presentapplication disclose utilizing the methods of the present applicationfor forming multi-track jogged layout for BEOL patterning, the presentapplication is not limited to only the formation of BEOL patterns.Instead, the present application can be used in forming other types ofstructures such as FEOL fin patterning.

FIG. 1 depicts an illustrative designed layout pattern 1 for anexemplary interconnect structure including varying types of lines andspaces having a pitch less than 40 nm with jogged features therebetween,i.e., cross-connections between the different line features. The linesand jogged features will be defined by a self-aligned quadruplepatterning process utilizing top and bottom mandrels to increase patterndensity by repeating the spacer formation and pattern transfer steps,which advantageously can be utilized to provide pitches less than 40 nm.The various types of lines and jogs can be further characterized bylocation relative to the top mandrel features 20L and 20R utilized inthe self aligned quadruple process to form the design layout pattern.The lines are designated α, β, and γ based on the location relative tothe top mandrel and the corresponding cross track jogs between thedifferent line features α, β, and γ can be classified as falling intoone of three general types: βγβ, βαβ and αβγ or γβα, wherein the firstand third positions refer to the uncut line and the second positionrefers to the cut line. By way of example, the βγβ cross track jogrefers to adjacent uncut β lines and a cut in the non-mandrel γ line toform a jog extending between adjacent bottom mandrel β lines.

As for the above nomenclature, the β lines are defined by the patternedbottom mandrel; the γ lines are defined by sidewall spacers of thepatterned bottom mandrel located underneath the top mandrels 20L and20R; and the α lines are those defined by elimination and are locatedunderneath neither the top mandrel nor the bottom-mandrel.

As will be discussed in greater detail below, the βγβ jog is formedsubsequent to backfilling a top mandrel spacing with a top non-mandrelmaterial by cutting the top mandrel (TM) with a gap smaller than 2 timesthe top spacer thickness. Because the cut defining the tips to tips ofthe top mandrel is smaller than twice the thickness of the top spacer,the spacer pinches and forms a bridge between portions of the bottommandrels that underlie the same top mandrel. The top non-mandrelmaterial is etch selective to both the top mandrel materials and the topspacer materials, wherein etching can be simultaneous done. The βαβ jogis claimed by backfilling the top mandrel space after a spacer etch witha filler material (non-mandrel) that is resistant (along with top spacermaterial) to the pull chemistry of the top non-mandrel and top mandrelas well as the top spacer material but can also be used as a mask foretching the bottom mandrel. The αβγ, γβα jogs are claimed by cuts in thebottom mandrel with the tips to tips larger than twice the thickness ofthe bottom spacer causing pinch off, thereby creating the αβγ, γβαconnections. In the embodiments that follow, FIGS. 2-10 depict methodsto achieve these different connections.

Referring now to FIGS. 2A and 2B, there is depicted an exemplarysemiconductor structure 10 for forming the designed layout pattern ofFIG. 1 comprising an interlayer dielectric layer (ILD) 12, a barrierlayer 14, a bottom mandrel layer 16, an insulator layer 18 and patternedtop mandrel structures 20L, 20R located on the insulator layer 18. Thepatterned top mandrel structures are lithographically patterned from aplanar top mandrel layer generally designated by reference numeral 20.

The ILD 12 may comprise any dielectric material including inorganicdielectrics or organic dielectrics. The dielectric material may beporous or non-porous. Some examples of suitable dielectric materialsinclude, but are not limited to: SiO₂, silsesquioxanes, carbon dopedoxides (i.e., organosilicates) that include atoms of Si, C, O and H,thermosetting polyarylene ethers, or multilayers thereof. The term“polyarylene” is used to denote aryl moieties or inertly substitutedaryl moieties which are linked together by bonds, fused rings, or inertlinking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide,carbonyl and the like. The ILD 12 may be deposited by PECVD proceduresas is generally known in the art. These patterned features correspond tothe subsequent interconnect vias (i.e., metal plugs between levels) andcan be aligned with underlying source and/or drain regions or over ametal gate structure defined by the particular substrate (not shown).The thickness of the ILD generally ranges from 50 nm to 70 nm, althoughlesser and greater thicknesses can also be employed.

The barrier layer 14 may be formed of metals such as titanium (Ti),tantalum (Ta), tungsten (W), compounds such as titanium nitride andtantalum nitride, alloys such as TiW, doped metals such as titanium ortantalum doped with nitrogen (Ti(N) or Ta(N)) and bilayers such as Ti/Wor Ta/TaN. In one or more embodiments, the barrier layer 14 is titaniumnitride, which may be deposited through conventional depositionprocesses such as, for example, a plasma vapor deposition process suchas R.F. sputtering. The thickness of the barrier layer 14 may varydepending on the exact means of the deposition process as well as thematerial employed. The titanium metal liner layer is used to provideadhesion between subsequent overlying structures, such as a tungstenplug structure, and ILD layer 12, as well as supplying the neededtitanium, for subsequent formation of a titanium silicide layer, ifdesired. The thickness of the barrier layer 14 can be from 50 nm to 200nm, although lesser and greater thicknesses can also be employed.

The bottom mandrel layer 16 may be formed of amorphous silicon. However,it should be noted that other materials (e.g., germanium, silicongermanium) may also be used for the mandrels so long as there is an etchselectivity with respect to subsequently formed sidewall spacersthereon, which will be discussed in greater detail below. The thicknessof the bottom mandrel layer generally ranges from 40 nm to 100 nm,although lesser and greater thicknesses can also be employed.

The patterned mandrel structures 20L, 20R, like the bottom mandrel, mayalso be formed of amorphous silicon although, as noted above, othermaterials (e.g., germanium, silicon germanium) may also be used for themandrels so long as there is sufficient etch selectivity with respect tosubsequently formed sidewall spacers thereon. As shown, the top mandrellayer is first lithographically patterned to form the mandrel structures20L and 20R.

The lithography process for forming the top mandrel pattern maycomprise, for example, introducing electromagnetic radiation such asultraviolet light through an overlay mask to cure a photoresist material(not shown). Depending upon whether the resist is positive or negative,uncured portions of the resist are removed to form a first resistpattern including openings to expose portions of the top mandrel layer.

The material defining photoresist layer may be any appropriate type ofphoto-resist materials, which may partly depend upon the device patternsto be formed and the exposure method used. For example, material ofphoto-resist layer may include a single exposure resist suitable for,for example, argon fluoride (ArF); a double exposure resist suitablefor, for example, thermal cure system; and/or an extreme ultraviolet(EUV) resist suitable for, for example, an optical process. Photoresistlayer may be formed to have a thickness ranging from about 30 nm toabout 150 nm in various embodiments. The resist pattern may be formed byapplying any appropriate photo-exposure method in consideration of thetype of photo-resist material being used.

The photoresist pattern is then anisotropically etched such as byreactive ion etching (RIE) to define the first mandrel shapes 20L and20R. The top mandrel shapes 20L and 20R have nearly vertical etch slopesor nearly vertical contact angles. By use of the terms “nearly verticaletch slope” or “nearly vertical contact angle” is meant an angle definedby the sidewall of the opening being formed of at least 80°, preferablyabout 90°, with the plane of the top mandrel layer being anisotropicallyetched.

The etching apparatus used in carrying out the anisotropic etch maycomprise any commercially available reactive ion etching (RIE)apparatus, or magnetically enhanced reactive ion etching (MERIE)apparatus, capable of supporting a wafer of the size desired to beetched in which gases of the type used herein may be introduced at theflow rates to be discussed and a plasma maintained at the power levelsrequired for the process. Such apparatus will be generally referred toherein as RIE apparatus, whether magnetically enhanced or not. Examplesof such commercially available apparatus include the Precision 5000magnetically enhanced reactive ion etcher available from AppliedMaterials, Inc.; the Rainbow reactive ion etcher by Lam; the reactiveion apparatus by Tegal Company; and the Quad reactive ion etcher byDrytek.

As shown in FIGS. 3A and 3B, a portion of the top mandrel structure 20Ris then cut mask etched to form cut 22 (i.e., forms a gap within topmandrel line 20R), which generally defines the top mandrel tips in topmandrel structure 20R as shown more clearly in the top down schematic ofFIG. 3A. The gap defined by tips to tips of top mandrel 20R (defined bythe cut 22) is smaller than twice the thickness of top dielectric spacer40 (shown and described with reference to FIGS. 4A and 4B, which willsubsequently be used cause a pinch off bridge between the two bottommandrels that underlie the same top mandrel for forming the βγβ crossconnections in the designed pattern of FIG. 1.

In FIGS. 4A and 4B, a top dielectric spacer 40 is formed on thesidewalls of the top mandrel features 20L and 20R and within the gapprovided by cut 22 of top mandrel 20R so as to form the βγβ connectiongenerally designated by reference numeral 44. In addition, the spacesremaining after formation of the top dielectric spacer are backfilledwith a top non-mandrel material 42.

An exemplary top spacer-forming layer 40 is conformally deposited suchas by atomic layer deposition (ALD), plasma-enhanced chemical vapordeposition (PECVD), a low pressure chemical vapor deposition (LPCVD), oranother chemical vapor deposition process. An exemplary spacer-forminglayer contacts the upper surface of the upper hard mask layer 18, andthe top surfaces and sidewalls of the top mandrels including the gapdefined by cut 22. The dielectric spacer-forming layer may be formed ofsilicon nitride, silicon dioxide, or any type of organic or inorganicmaterial having etch selectivity with respect to top mandrels 20L and20R. The thickness of the top spacer layer is set by the target pitchline as this thickness generally determines the bottom mandrel, which inturn defines the space in which metallization is utilized to form theinterconnect. The space is generally one half the pitch in mostembodiments.

The top spacer layer 40 is then etched to barrier layer 18 to provide ametal spacer material on exposed sidewalls of the patterned top mandrelfeatures 20L and 20R and between the tips defined by cut 22 in mandrelfeature 20R as shown. The remaining space between the patterned topmandrel with the sidewall top metal spacers is then backfilled with atop non-mandrel filler material 42 that in turn can be cut selected tothe top mandrel and top spacer so as to form a βαβ jog upon subsequentpatterning of the bottom mandrel. The non-mandrel filler material 42 iscoplanar with the uppermost surfaces of the top mandrel features 20L and20R.

Exemplary non-mandrel filler materials 42 include various spin on filmsincluding, but not limited to, silicon containing anti-reflectivecoatings (ARC) films, metallic spin on films, spin on films that containrare earth elements, and the like.

As shown in FIGS. 5A and 5B, the top non-mandrel backfill material 42 isthen selectively etched to the barrier layer 18 to form cut 50. Itshould be apparent that there is a edge placement error (EPE) isminimized due to the 4× pitch and top non-mandrel to top mandrel etchselectivity. EPE is measured as the difference between the intended andprinted features in a layout.

In FIGS. 6A and 6B, the top non-mandrel cut 50 is refilled with fillermaterial 52 to form the βαβ jog for the designed layout pattern 10.Filler material 52 is selected to have selectivity similar to that ofthe sidewall spacers 40. In some embodiments, filler material 52 is thesame as the material used for forming top spacer layer 40. Filling cut50 in the top non-mandrel 42 with another filler material allows thepull of the top mandrel and the top non-mandrel backfill materialrelative to the top spacer 40 and the top non-mandrel tip to tip fill 52for forming the βαβ connection.

In FIGS. 7A and 7B, the top non-mandrel material 42 and top mandrels20L, 20R are pulled leaving spacer features 40, the βαβ connections 52,and the βγβ connections 44 in the top mandrel layer 20.

In FIGS. 8A, 8B, and 7 c, an anisotropic transfer etch is made totransfer the patterned spacers 40, the βαβ connections 52 and βγβconnections 44 to the bottom mandrel layer 16 using layer 14 as an etchstop. As shown more clearly in FIG. 8B, the βαβ connections aretransferred to the bottom mandrel along with the corresponding spacerline segments 40. In FIG. 8C, it is the βγβ connections that aretransferred to the bottom mandrel 16 along with the corresponding spacerline segments.

In FIGS. 9A and 9B, the bottom mandrel is selectively cut by cut 62,which can be used to form the αβγ and γβα connections generallydesignated by reference numeral 64, shown in FIGS. 10a , 10B. In one ormore embodiments, the tips to tips defined by cut 62 is larger thantwice the thickness of a bottom spacer layer 60, which will subsequentlycause a pinch off and hence the αβγ and γβα jog connections in thedesigned layout pattern of FIG. 1.

In FIGS. 10A and 10B, the bottom spacer layer 60 (such as silicondioxide or silicon nitride, Si₃N₄, for example) is then deposited ontothe patterned bottom mandrel layer 16. In accordance with one exemplaryaspect, the bottom spacer 60 may deposited through a conformal filmdeposition process, such as, for example, atomic layer deposition (ALD),molecular layer deposition (MLD), or quasi-ALD or MLD processes. Thebottom spacer layer 60 is then etched to the layer 14 to provide aspacer material abutting sidewalls of the patterned bottom mandrelfeatures 16. The bottom mandrel 16 is then pulled to provide thepatterned structure shown in FIG. 10A, which is then subjected to ametallization process to form the interconnect structure shown in thedesigned layout of FIG. 1.

Advantageously, the present invention provides for greater alignmenttolerances in patterning the jogs by providing the cut in the firstmandrel of a self-aligned quadruple patterning process.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of onemore other features, integers, steps, operations, element components,and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

The flow diagrams depicted herein are just one example. There may bemany variations to this diagram or the steps (or operations) describedtherein without departing from the spirit of the invention. Forinstance, the steps may be performed in a differing order or steps maybe added, deleted or modified. All of these variations are considered apart of the claimed invention.

While the preferred embodiment to the invention had been described, itwill be understood that those skilled in the art, both now and in thefuture, may make various improvements and enhancements which fall withinthe scope of the claims which follow. These claims should be construedto maintain the proper protection for the invention first described.

What is claimed is:
 1. An interconnect structure including multi-trackjogs produced by a self-aligned quadruple patterning process having apitch less than 40 nm, the interconnect structure comprising three typesof lines: a β line defined by a patterned bottom mandrel formed in theself-aligned quadruple patterning process; a γ line defined by locationunderneath a top mandrel formed in the self-aligned quadruple patterningprocess; and an α line defined by elimination located underneath neitherthe top mandrel or the bottom mandrel formed in the self-alignedquadruple patterning process.
 2. The interconnect structure of claim 1,wherein the multitrack jogs are selected from a group consisting of: aβγβ jog; a βαβ jog; an αβγ jog; a γβα jog, and combinations thereof. 3.The interconnect structure of claim 1, wherein the multitrack jogs areformed by a single cut.
 4. The interconnect structure of claim 2,wherein the βγβ jog is formed by cutting at least one of the top mandrelstructures to provide a gap corresponding to a γ jog, wherein the gap issmaller than two times a thickness of the top spacer structure; andfilling the gap with the dielectric material.
 5. The interconnectstructure of claim 2, wherein the βαβ jog are formed by cutting at leastone of the top non-mandrel backfilled spaces to provide a gapcorresponding to an α jog, wherein the gap is filled with a fillermaterial etch selective to the top mandrel and the top non-mandrelmaterial.
 6. The interconnect structure of claim 2, where the αβγ andthe γβα jogs are formed by cutting at least one of the bottom mandrelstructures to provide a gap corresponding to a β jog; forming a bottomspacer structure with a bottom dielectric material adjacent to sidewallsof the top mandrel features, wherein the gap is larger than two times athickness of the bottom spacer structure.
 7. The interconnect structureof claim 1, wherein the top non-mandrel material comprises siliconcontaining anti-reflective coatings (ARC) spin on films, metallic spinon films, or spin on films that contain rare earth elements.
 8. Theinterconnect structure of claim 4, wherein the dielectric materialcomprises silicon nitride, or silicon dioxide.
 9. The interconnectstructure of claim 1, wherein the bottom dielectric material is aconformally deposited by atomic layer deposition or molecular layerdeposition.